1. Field of Invention
The present invention relates to an integrated circuit chip pin-out designation method and, more particularly, to a pin-out designation method for package board codesign.
2. Description of the Related Art
Because of deep submicron (DSM) technology, chips now contain more functionality and are driven to higher performance levels. Consequently, with more functionality on the chip, designers have to deal with higher I/O densities, more signals coming out of a chip and tighter geometries. This complicates design of packaging which accommodates chips, as well as the board which accommodates the packages. As a result, designing the chip, the package and the surrounding system creates advantages, but is also challenging. Recently, chip-package codesign has created attention. However, packageboard codesign is definitely not trivial and still needs more development.
FIG. 11 shows a typical interface design flow for an integrated circuit (IC) package-printed circuit board (PCB) codesign. IC designers finish the pin designation based on experience (rule-of-thumb). In order to tradeoff signal performance and package cost, the designers always take a few weeks to modify package size, rework package substrate and PCB layout, and then rearrange the pin-out. This conventional process can not efficiently estimate an accurate package size during designating pins for a flip-chip BGA and can possibly degrade signal performance due to the weakness on product experience and basic design concept. Furthermore, these costly reworks constantly postpone launch schedules of chips, thus lengthening the time to market (TTM).
The present invention provides a pin-out designation method for package board codesign to obviate or mitigate the shortcomings of the conventional pin-out designation method.